Flip Flop Interview Question Answer - 3

31	Describe the main difference between JK flip flop and SR flip flop.
	JK flip flop – SR flip flop The JK flip flop has no invalid state that of in the SR flip flop. There is one invalid state S = 1, R = 1 for NAND gated SR flip flop and S = 0, R = 0 for NOR gated SR latch. When J = 1 and K =1, the output toggles it means the output Q changes either 0 to 1 or 1 to 0.
32	Why the output of the JK flip flop toggles when input J = 1 and K = 1?
	The output Q and Q bar is feedback input K and input J respectively therefore the output toggles when input J = 1 and K =1 in the JK flip flop.
33	How to convert JK flip flop into T flip flop?
	The JK flip flop is converted into T flip flop by connecting J and K input together and labeled as T means toggle.
34	Which is the most versatile flip flop?
	JK flip flop
35	When the T flip flop toggles?
	When the input T is set 1 ( one ), the T flip flop toggles.
36	Describe the function of asynchronous inputs? Which are the different asynchronous inputs.
	Function of Asynchronous Inputs The asynchronous inputs can be used to SET the flip flop to state 1 or RESET the flip flop 0 states without considering any input conditions. We can say that the asynchronous inputs override the inputs. The asynchronous input may be PRESET ( PRE ) or DC SET or direct set ( SD ) , DC CLEAR, CLEAR or direct reset ( RD ).
37	Define : Propagation delay time
	Propagation delay time It is defined as the time interval between the time of triggering edge or asynchronous inputs and the time at which the output makes transition. It is given in the range of Micro second to Neno seconds. It is measured between 50% points on the input and output waveform.
38	Define : Maximum clock frequency
	Maximum clock frequency It is defined as the highest frequency at which a flip flop can triggered reliably.
39	Define : Set up time
	Set up time It is defined as the minimum time for which the control levels needs to maintain constant at the input terminal of the flip flop prior to the arrival of triggering edge of clock pulse for reliable operation of the flip flop.
40	Define : Hold time
	Hold time It is defined as the minimum time for which the control levels needs to maintain constant at the input terminal of the flip flop after the arrival of triggering edge of clock pulse for reliable operation of the flip flop.
41	Explain the term clock skew. Describe the effect of it.
	Clock skew When a clock signal which is applied simultaneously to all flip flops in a synchronous system, the delay of the signal to various flip flops are caused by wiring between components and arrive of CLK inputs to flip flop at different times.  It is called as clock skew in the flip flop. If the skew time is minimal, a flip flop may get clocked before narrow input pulse arrives. Similarly if the clock pulse is delayed, the input of the flip flop may have changed before the clock pulse arrives. There is race between two signals which is terms as time race.
42	State the holding time of edge triggered flip flop.
	The holding time of edge triggered flip flop may be less than 5 Neno second.
43	Which flip flop has no holding time?
	Master slave flip flop  or Pulse triggered flip flop
44	Why the master slave flip flop is also called as Pulse triggered flip flop?
	The master slave flip flop is also called as pulse triggered flip flop because the length of the time required for its output to change state equal to width of one clock pulse.
45	How to avoid time delay problem in the master slave flip flop?
	Time delay Problem The time delay problem in the master slave flip flop is avoided by introducing a known time delay between the time that the flip flop responds to clock pulse and time the response appears at its output.

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